Test and debug strategy of the PNX8525 NexperiaTM digital video platform system chip

Decreasing feature sizes and increasing customer demand for more functionality have forced design teams to re-use design blocks and application platforms. As a result, re-use of test, design-for-test and design-for-debug for large system chips is becoming increasingly important and increasingly necessary. In this paper, the test and debug features of the Nexperia PNX8525 chip are presented. The PNX8525 chip is a large system chip for the consumer electronics market. The impact of corebased testing is discussed, at both the core-level and the top-level, together with the design-for-debug implementation on this multiple clock domain chip.